1. Field of the Invention
The present invention generally relates to a semiconductor device package, and more particularly, to a semiconductor device package comprising inner leads having slots formed on an upper surface of the inner leads in contact with an adhesive layer.
2. Description of the Related Art
Semiconductor chip packages have been developed to increase the mounting density of the semiconductor chip on a substrate such as a printed circuit board. However, for conventional semiconductor device packages having a die pad, since the die pad is disposed at the central region inside the package body and separated from a plurality of inner leads by a designated distance, the density of the semiconductor chip inside the package is very low.
Chip-on-Lead (COL) type packages have structures in which the die pad is removed and the bottom surface of the semiconductor chip is directly attached to the upper surfaces of the inner leads. Therefore, the density of the semiconductor chip inside the package is higher than that of the conventional package described above.
A conventional COL semiconductor chip package is depicted in FIGS. 1, 2 and 3. FIG. 1 shows a conventional COL package in a partially cut away perspective view; FIG. 2 is a cross sectional view taken along the line 2--2 of FIG. 1; and FIG. 3 is a cross sectional view taken along the line 3--3 of FIG. 1.
Referring to FIGS. 1, 2 and 3, the bottom surface 10b of a semiconductor chip 10 is directly attached to respective upper surfaces 30u of a plurality of inner leads 30 of the lead frame, which is aligned under the bottom surface 10b of the semiconductor chip 10, by an adhesive means 20 such as a polyimide tape. The semiconductor chip 10 is electrically connected to the inner leads 30 disposed on the outside of the semiconductor chip 10 by electrical connection means such as bonding wires 50.
Further, the semiconductor chip 10, the inner leads 30, and the electrical connection means including the bonding wires 50 are encapsulated with an encapsulant, such as an epoxy molding compound (EMC), to form an individual package body 60 that is protected from hostile environments. The outer leads 40 extend from the encapsulated package body 60, and are bent into a J-shape suitable to be mounted on a substrate.
FIG. 4A is a schematic view showing the flow of the EMC in the encapsulation step of the package, as viewed along the same direction as the cross section directional view of FIG. 3. FIG. 4B is a magnified view of portion E of FIG. 4A.
Referring to FIGS. 4A and 4B, the inner leads 30 and the semiconductor chip 10 are located within cavities 312 and 412 formed between an upper mold die 310 and a lower mold die 410. The cavities 312 and 412 are encapsulated with an encapsulant which flows through a gate 414 of the lower mold die 410.
In FIGS. 4A and 4B, the arrows indicate the flow direction of the encapsulant. The encapsulant initially collides with the right surface 30r of the inner lead 30, which decreases the flow velocity of the encapsulant stream. The encapsulant then flows along the bottom surface 30b of the inner leads 30, and finally to the left side 301 of the inner leads 30. As shown in FIG. 4B, the encapsulant flow is disturbed or turbulent on the left surface 301 due to the difference in the flow velocity. Again, the upper surface 30u of the inner leads 30 is attached to the bottom surface 10b of the semiconductor chip 10.
In particular, in situations were the pitch between the inner leads is very fine, or where there are a large number of inner leads, the turbulence of the encapsulant becomes more serious. Such turbulence produces internal voids and incomplete encapsulation. These internal voids swell when penetrated by a vapor, which is introduced during reliability testing carried out under severe conditions such as high temperature, pressure and humidity. An incomplete encapsulation of the package body also causes the mechanical strength of the package to deteriorate.